1. Field of the Invention
The present invention is related to an improvement of the semiconductor device provided with a programmable impedance output buffer driver for adjusting the impedance of the output buffer of the semiconductor device.
2. Description of the Related Art
In the recent years, along with increasing frequencies of input/output operations in the field of the semiconductor integrated circuits, it becomes increasingly important to avoid matching problems caused between the impedance of an output buffer and the impedance of a transmission line formed on a printed circuit board (PCB).
In the prior art semiconductor devices, however, if there exists a mismatch between the impedance of the bus lines of the system and the impedance of the output buffer of the device which is connected to the bus lines, undesirable reflection waves take place at the interface so that it is impossible to realize high speed data transmission and high speed operation of the system bus due to the reflection waves.
A new technique called the programmable impedance output buffer driver has been proposed, wherein, even if the environment is changed, the impedance of the output buffer can be finely adjusted to an 1/n of the impedance as prepared between a ZQ pad and VSS by a user. Typically, the number n is an integer, for example, five. This technique becomes one of the important circuit techniques for realizing the high speed data transmission.
FIG. 1 is a block diagram showing the circuit configuration of the prior art programmable impedance output buffer driver. An external resistor 50 is connected between the lower power potential level VSS (e.g., the ground potential) and the ZQ pad to which is applied, from the external impedance monitoring load circuit, a half reference potential of the higher power potential (VDDQ) as applied to the output buffer 5. The impedance of a dummy output buffer 2 is adjusted to the impedance of the resistance value RQ of the external resistor 50 by the impedance adjustment control circuit 3.
Thereafter, a data update control circuit 4 outputs an adjustment data of the dummy output buffer 2 to the output buffer 5 in a certain timing so that the impedance of the output buffer 5 is set as the 1/n of said external resistor 50 to update the output impedance.
A sampling clock generating circuit 6 generates sampling clocks for controlling the opening and closing operation of the register of the impedance adjustment control circuit 3 and the data update control circuit 4 in order to supply the sampling clocks to the impedance adjustment control circuit 3 and the data update control circuit 4.
Meanwhile, both the dummy output buffer 2 and the output buffer 5 are composed of a plurality of transistors which are turned on/off in order to change the impedance thereof. Accordingly, the data update control circuit 4 outputs the on/off signals, e.g., four bit signals A0, A1, A2 and A3 (i.e., the adjustment data) for turning on or off the plurality of the transistors of the dummy output buffer 2 in order to adjust the impedance of the output buffer 5.
FIG. 2 is a block diagram showing the exemplary circuits of the external impedance monitoring load circuit 1, the dummy output buffer 2 and the output buffer 5. The information of the resistance value RQ of the external resistor 50 is extracted as the potential level VZQ. In this case, the four bit signals A0, A1, A2 and A3 are adjusted with the high level "1" and the low level "0" in order to adjust the pad potential of the ZQ pad equal to the potential VEVAL so that the resistance value RQ of the external resistor 50 is made equal to the impedance of the dummy output buffer 2.
As described above, the impedance of the output buffer 5 of the programmable impedancne output buffer driver is controlled to maintain the 1/n of the resistance value RQ of the external resistor 50 by updating the four bit signals A1, A1, A2 and A3 in a certain timing by means of the data update control circuit 4. There is a problem, however, that when the programmable impedance output buffer driver can not correctly operate for some reason irrespective of the resistance value RQ of the external resistor 50 maintained at a constant value, resulting in a fluctuating the impedance of the output buffer 5, it is impossible to evaluate the operation speed of devices such as a memory. This tends to affect the efficiency of other test items for this device.